At the end of the workshop, participants will be able to:
Understand the VLSI and FPGA design flow using industry-standard tools such as Cadence and Xilinx Vivado.
Apply HDL concepts (Verilog/VHDL) to design, simulate, and verify digital circuits in both ASIC and FPGA environments.
KPRIET – An AI Integrated Campus
Preparing future-ready engineers with AI-integrated teaching and learning. KPRIET integrates Artificial Intelligence across teaching, learning, research and innovation to create a smarter, future-ready campus experience for students and faculty.